bus architecture
基本解釋
- 總線結(jié)構(gòu)
- 總線體系結(jié)構(gòu)
英漢例句
- USB as a powerful and flexible bus architecture, can well meet the requirements of a new TV set-top boxes.
USB作為功能強(qiáng)大而且靈活的總線結(jié)構(gòu),能很好的適應(yīng)新型電視機(jī)頂盒的要求。 - Traditionally only one CPU is in the bus architecture, With the development system theory, multi-CPU architecture tends to be more advantageous and attractive.
但是隨著系統(tǒng)的發(fā)展,多CPU體系是更大規(guī)模發(fā)展的趨勢,但總線結(jié)構(gòu)的原始構(gòu)思是基于單一CPU的,傳統(tǒng)總線結(jié)構(gòu)無法滿足發(fā)展的需求。 - The Adapter-Based Software-Bus Architecture(ABSBA) has the properties of clearness and simpleness, which makes it convenient to specify the relations between components.
基于適配器的軟件總線結(jié)構(gòu)ABSBA具有結(jié)構(gòu)清晰、單一的特征,易于規(guī)范構(gòu)件間的關(guān)聯(lián)。 - Things like the number of computer instructions per clock cycle, the bandwidth of the RAM bus, and the overall efficiency of the architecture are at least as important as the raw clock speed at which a processor runs.
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雙語例句
權(quán)威例句
詞組短語
- bus s architecture 總線結(jié)構(gòu)
- bus topology architecture 總線拓樸結(jié)構(gòu)
- DBMA Direct Bus Master Architecture 直接總線主體系結(jié)構(gòu)
- Advanced Microcontroller Bus Architecture 高級(jí)微控制器總線架構(gòu);高級(jí)微處理器總線架構(gòu);總線結(jié)構(gòu)
- unified bus architecture 統(tǒng)一總線結(jié)構(gòu)
短語
專業(yè)釋義
- 總線結(jié)構(gòu)
In all kinds of On-chip Buses available in the market, Advanced Microcontroller Bus Architecture (AMBA) which is designed and standardized by ARM company is one of the most popular industrial standards.
在市場現(xiàn)有的各種片內(nèi)總線中,由ARM公司開發(fā)的高級(jí)微處理器總線架構(gòu)(AMBA)市場占有率最高,成為一種最流行的工業(yè)標(biāo)準(zhǔn)片內(nèi)總線結(jié)構(gòu)。 - 總線型架構(gòu)
- 匯流排架構(gòu)
- 總線結(jié)構(gòu)
Not only IP design itself should be designed carefully with low energy comsumption, but the bus architecture connecting IPs is important too. CMOS power management IP can save energy for system by supporting several power modes when integrated into SOC.
不僅IP設(shè)計(jì)本身要實(shí)現(xiàn)低功耗設(shè)計(jì),連接IP的總線結(jié)構(gòu)也是低功耗設(shè)計(jì)的考慮重點(diǎn),集成在SOC內(nèi)部的電源管理IP通過對(duì)系統(tǒng)功耗模式提供硬件支持來降低功耗。