bus transceiver

基本解釋

The problems of backplane bus design, such as the driver, timing and signal integrate, have solved by using the GTL transceivers, phase adjustment of the clock and combined match techniques.
采用新型的GTL總線收發(fā)器、時鐘相位調節(jié)和組合式匹配等技術措施，解決了總線設計的驅動、時序和信號完整性問題。
The memory system of dual channel A/D automatic acquisition is studied in this paper. Using transceivers and gating controllers, the data bus and address bus of RAM are respectively controlled.
本文研究了雙通道A/D自動采集存儲系統(tǒng)，利用數(shù)據(jù)收發(fā)器及數(shù)據(jù)選通控制器分別控制RAM的數(shù)據(jù)線及地址控制線。