clock flip-flop

基本解釋

With the mechanism of clock flip- flop, data can be extracted automatically.
系統(tǒng)采用時(shí)鐘觸發(fā)機(jī)制實(shí)現(xiàn)了數(shù)據(jù)的自動(dòng)抽取過程；
Especially, the clock-racing multi-threshold flip-flop can decreases the leakage power and the power dissipation of clock network.
特別是多閾值時(shí)鐘競(jìng)爭(zhēng)型觸發(fā)器，不僅可以降低電路的漏電流功耗，還能降低電路的時(shí)鐘網(wǎng)絡(luò)的功耗。
The results of simulation suggest that the designed FK-LSCDFF has correct logic function, and reduces 17% powedissipation compared with conventional low-swing clock double-edge-triggered flip-flop.
模擬結(jié)果表明所設(shè)計(jì)的觸發(fā)器具有正確的邏輯功能，跟傳統(tǒng)的時(shí)鐘低擺幅雙邊沿觸發(fā)器相比，降低近17%的功耗。