clock signal frequency

基本解釋

Direct Digital Synthesize (DDS) is used to generate clock signal at any frequency so that data generator can output data at any rate.
著重分析采用直接數(shù)字合成（DDS）技術產(chǎn)生任意頻率時鐘信號的方法，實現(xiàn)數(shù)據(jù)發(fā)生器以任意碼率輸出數(shù)據(jù)；
A first circuit is coupled with the first end of the quartz oscillator and is used for generating a first clock signal with a fixed frequency according to the first signal.
一第一電路耦接于上述石英振蕩器的上述第一端，用以根據(jù)上述第一信號產(chǎn)生具有固定頻率的一第一時鐘信號。
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A second circuit is coupled with the second end of the quartz oscillator and is used for generating a second clock signal with a variable frequency according to the second signal.
一第二電路耦接于上述石英振蕩器的上述第二端，用以根據(jù)上述第二信號產(chǎn)生具有可變頻率的一第二時鐘信號。
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