digital down converter

基本解釋

This paper studies the high decimation ratio of digital down converter, and especially analyzes the multi-stage decimation algorithm based on CIC filter and HB filter.
該文研究了高倍抽取的數(shù)字下變頻設(shè)計，重點分析了基于級聯(lián)積分梳狀濾波器和級聯(lián)半帶濾波器的多級抽樣頻率算法。
The design of hardware module includes A/D converter, DDC (Digital Down Converter) and DSP. The design and application of AD6640 and AD6624 are fully discussed in this part.
模塊的硬件設(shè)計主要包括：A／D轉(zhuǎn)換器、數(shù)字下變頻器（DDC）以及DSP，詳盡討論了A／D 器件AD6640和DDC 器件AD6624的設(shè)計和應(yīng)用；
The basic concept and architecture of software radio is introduced in this paper. And a type of software radio receiver based on programmable digital down converter(DDC)-HSP50214B is presented.
介紹了軟件無線電的基本思想及結(jié)構(gòu)，提出了一種基于可編程數(shù)字下變頻器HSP50214B的中頻軟件無線電接收系統(tǒng)的設(shè)計方案。

數(shù)字下變頻器
In this paper, a new structure of Coordinate Convert Module in Digital Down Converter is presented which is based on CORDIC algorithm.
本文介紹了一種基于CORDIC算法的數(shù)字下變頻器(DDC)中坐標(biāo)變換模塊的結(jié)構(gòu)以及該結(jié)構(gòu)的ASIC實現(xiàn)。