logic gate level

基本解釋

Using gate level modeling might not be a good idea for any level of logic design.
使用門(mén)級(jí)建模對(duì)于任何邏輯設(shè)計(jì)都不是一個(gè)好的設(shè)計(jì)。
Level restoration pass-transistor logic is proposed for low speed cell while dynamic transmission gate logic for high speed cell.
低速單元采用帶有電平恢復(fù)的傳輸管邏輯實(shí)現(xiàn)，高速單元采用動(dòng)態(tài)傳輸門(mén)邏輯實(shí)現(xiàn)。
The pre-functional cell of standard buffered FET logic (BFL) adopted by the gate array possesses nine logic functions, two different kinds of driving capabilities, and the level control ability.
此門(mén)陣列采用的BFL預(yù)功能級(jí)標(biāo)準(zhǔn)邏輯單元，具有九種組合邏輯功能及兩種不同選擇的驅(qū)動(dòng)能力，并具有輸出電平調(diào)節(jié)功能。