synchronizing circuit

基本解釋

Design of a Circuit Synchronizing the Byte Clock with the Parallel Data in the Deserializer;
在串并轉(zhuǎn)換接收器中，并行數(shù)據(jù)在字節(jié)時(shí)鐘的作用下并行輸出。
A synchronizing nonalltonomus chaotic circuit is presented with RC-QP Amp. It can be used to demonstrate experiment teaching of chaotic theory.
本文給出一種用普通的電阻、電容和運(yùn)算放大器實(shí)現(xiàn)的非自治混沌信號(hào)發(fā)生器電路，適用于進(jìn)行混沌理論的演示實(shí)驗(yàn)教學(xué)。
In the circuit design, unit current source arrays and digital synchronizing cells are used to improve the matching and dynamic range of DAC.
電路設(shè)計(jì)中使用單位電流源陣列和數(shù)字同步控制單元來(lái)提高電流源的匹配性和動(dòng)態(tài)范圍；