virtual memory address translation

基本解釋

Writing process is complete page-based virtual memory address translation process management and simulation page fault handling.
編寫程序完成頁式虛擬存儲管理中地址轉(zhuǎn)換過程和模擬缺頁中斷的處理。
As mentioned before, memory addresses that are referred by a process are virtual addresses and require translation to the physical address.
如前所述，進程所引用的內(nèi)存地址是虛擬地址，需要將其轉(zhuǎn)換成物理地址。
In order to optimize performance, including speed and the usage of its memory, CPU usually hires a Translation Lookaside Buffer(TLB) to translate the virtual address into physical address.
為了提高CPU的速度和更有效的管理物理內(nèi)存，一般都采用轉(zhuǎn)換查找緩沖器（TLB）將虛擬地址轉(zhuǎn)換為物理地址。