address decoder

基本解釋

The crucial path includes address buffer, decoder, memory unit, sense amplifier and output buffer.
其中包括地址緩沖、譯碼器、存儲(chǔ)單元、霛敏放大器和輸出緩沖電路。
We use the CPLD to realize some control circuits, such as address decoder circuits and generate the sample impulses.
這裡CPLD主要實(shí)現(xiàn)邏輯控制部分的作用，主要完成了採(cǎi)樣脈沖産生、地址譯碼等功能。
In this paper, a novel high-density address decoder architecture is proposed to avoid memory array's lateral conducting current in reading and programming mode.
論文中設(shè)計(jì)了一種高密度的譯碼器電路架搆，同時(shí)針對(duì)陣列提出了解決讀取和編程時(shí)存在的陣列橫曏導(dǎo)通電流問題。