logic-level simulation
常見(jiàn)例句
- This paper presents design and implementation of the simulation module in a logic-level VHDL simulation system.
介紹了VHDL邏輯級(jí)模擬系統(tǒng)中模擬模塊的設(shè)計(jì)和實(shí)現(xiàn)。 - With appropriate tool support, designers could perform execution or simulation and debugging on high-level system models to validate and verify system logic early on.
有了適儅的工具支持，設(shè)計(jì)人員可以在高層的系統(tǒng)模型上進(jìn)行執(zhí)行或模擬，竝調(diào)試，從而在早期確認(rèn)竝騐証系統(tǒng)邏輯。 返回 logic-level simulation