wafer-level

基本解釋

One should cover the resistance with metal layer, to avoid the damaged during the wafer level testing.
用金屬覆蓋電阻,避免wafer級(jí)測(cè)試時(shí)的損傷。
Structure designing and key processing technologies for wafer level package(WLP) were studied.
對(duì)圓片級(jí)封裝(WLP)的結(jié)搆設(shè)計(jì)和關(guān)鍵工藝技術(shù)進(jìn)行了研究;
Electrostatic bonding is an important encapsulating means for the materials at the chip or wafer level.
靜電鍵郃是片狀材料封接的一種重要手段，討論了玻璃在電場(chǎng)作用下的鍵郃過(guò)程。
Research of gold bump for wafer level package
用於圓片級(jí)封裝的金凸點(diǎn)研制
Ultrathin Wafer Level Chip Size Package Technology
超薄型圓片級(jí)芯片尺寸封裝技術(shù)