clock jitter

常見例句

The effect of clock jitter and phase noise on data acquisition system performance is more profound as the increase of sampling frequency and the bit of A/D converter.
隨著采樣頻率和A/D變換器位數(shù)的增加，時鐘抖動和相位噪聲對數(shù)據(jù)采集系統(tǒng)性能的影響更加顯著。
Based on Gaussian random process model and continuous-time system in time domain , this paper analyzes the effect on baseband and intermediate frequency sampling due to clock jitter.
該文從時域連續(xù)信號角度出發(fā)，按照高斯隨機過程模型，分析了時鐘抖動對基帶和中頻線性調頻信號信噪比的影響并給出了近似公式。
jeit.ie.ac.cn
The Chip-Sync technology has been used to ensure the latch of high-speed signal, and we use high accuracy clock management chips and design reasonable clock way to strict control the clock jitter.
該系統(tǒng)采用了片同步技術實現(xiàn)了采樣后高速數(shù)字信號的可靠鎖存，采用高精度的時鐘管理芯片和設計合理的時鐘路徑對時鐘抖動做了嚴格控制。