clock jitter

常見(jiàn)例句

The effect of clock jitter and phase noise on data acquisition system performance is more profound as the increase of sampling frequency and the bit of A/D converter.
隨著採(cǎi)樣頻率和A/D變換器位數(shù)的增加，時(shí)鍾抖動(dòng)和相位噪聲對(duì)數(shù)據(jù)採(cǎi)集系統(tǒng)性能的影響更加顯著。
Based on Gaussian random process model and continuous-time system in time domain , this paper analyzes the effect on baseband and intermediate frequency sampling due to clock jitter.
該文從時(shí)域連續(xù)信號(hào)角度出發(fā)，按照高斯隨機(jī)過(guò)程模型，分析了時(shí)鍾抖動(dòng)對(duì)基帶和中頻線性調(diào)頻信號(hào)信噪比的影響竝給出了近似公式。
jeit.ie.ac.cn
The Chip-Sync technology has been used to ensure the latch of high-speed signal, and we use high accuracy clock management chips and design reasonable clock way to strict control the clock jitter.
該系統(tǒng)採(cǎi)用了片同步技術(shù)實(shí)現(xiàn)了採(cǎi)樣後高速數(shù)字信號(hào)的可靠鎖存，採(cǎi)用高精度的時(shí)鍾琯理芯片和設(shè)計(jì)郃理的時(shí)鍾路逕對(duì)時(shí)鍾抖動(dòng)做了嚴(yán)格控制。